Scalable superconducting quantum processors require Josephson junctions (JJs) with tightly controlled electrical characteristics and high reproducibility, since the JJ normal-state resistance is closely linked to the Josephson energy and therefore to qubit frequency allocation. In this seminar, I will present two recent studies showing that JJ behavior is governed not only by nominal junction area or oxidation conditions, but also by more subtle geometric and process-dependent factors. First, I will show that the normal-state resistance of Al/AlOx/Al junctions exhibits a systematic dependence on lateral dimensions and bottom-electrode thickness beyond simple area scaling, which can be captured by an edge-resistance model including perimeter-related contributions. Second, I will discuss how fabrication-history-induced disorder strongly affects junction resistance and wafer-scale reproducibility: even under identical oxidation conditions, junctions fabricated on bare wafers, lift-off–processed base layers, and dry-etched base layers display markedly different resistance statistics, indicating that nanoscale barrier disorder rather than average oxide thickness can dominate transport. Together, these results establish JJ geometry and upstream process history as key control knobs for deterministic qubit-frequency targeting and large-scale integration.